Intel details next-generation I/O spec

By Jerry Ascierto
EE Times
(08/31/01, 1:06 p.m. EST)

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SAN JOSE, Calif. — Intel Corp. provided a first look at technical details for Arapahoe, the third-generation system I/O expected to replace the ubiquitous PCI bus in a broad range of computer and communications systems, at the Intel Developer Forum this week. The chip interconnect is slated to hit the street in late 2003 at speeds of 2.5 Gbits/second per channel, bringing support for switching, packet prioritization and scalable bandwidth.

In tandem with the first look at Arapahoe, engineers have disclosed additional technical details about the PCI-X road map that will lead up to the third-generation I/O spec.

Already adopted by the influential PCI Special Interest Group (SIG), Arapahoe stands to become a broadly adopted conduit for data inside future desktop, notebook, server and eventually embedded systems. The technology is also expected to leapfrog competing approaches coming to market this year, including Motorola's RapidIO and Advanced Micro Devices' Hypertransport.

Arapahoe's 2.5 Gbits/s in each direction will provide a 200-Mbyte/s communications channel, almost doubling the classic PCI data rate. "We will extend this to 10 Gbits per second; I can see a clear path to that," said Ajay Bhatt, an architecture manager and principal engineer at Intel who heads the company's 3GIO development effort. "We're still working on the exact number, but it's an issue of cost of implementation. There is plenty of engineering being done now at 2.5.

"But as we try to balance multiple market segments, the stake in the ground is 2.5," Bhatt added. "And I've seen simulations run well in advance of 7 or 8 gig, and I know of some advanced coding techniques that could double that performance."

Announced at the spring Intel Developer Forum, the Arapahoe architecture was recently handed over to the PCI SIG, which will assume further governing and development of the spec as an industry standard. "Basically, it will fit into all of the places that PCI fits today," said Bob Gregory, director of desktop strategic planning for Intel.

Underscoring Arapahoe's multiple application base, 22 new members have joined the Arapahoe Working Group as key developers, a list that includes 3Com, ServerWorks, Agilent, ATI, Altera, LSI Logic, Nvidia and, conspicuously, AMD. While AMD's Hypertransport technology has been seen as a rival to Arapahoe, the company's involvement in the spec's development suggests otherwise.

"We never intended Hypertransport, when we were developing it, to be a replacement for PCI," said Gabrielle Sartori, president of the Hypertransport Consortium, comprising such companies as Apple, Nvidia, MIPS and Transmeta "We will support 3GIO just as we support PCI-X; it really makes no difference to us."

But not all interconnect standards will play so well together. "Everything that's been said about 3GIO can be said about any serial interconnect — it's fast, it's packetized — so what?" said Tom Cox, director of strategic planning for Tundra Semiconductor and a co-developer of the RapidIO spec who now helps steer the RapidIO trade organization. The industry is still waiting to hear further details on 3GIO, he said. "I see 'evolutionary' and 'revolutionary' on opposite ends of the spectrum; you're either evolutionary and you bring the path forward, or you do something that breaks the mold. I don't see anything revolutionary in that manner here."

In his keynote address at the Intel Developer Forum, Louis Burns, an Intel vice president and general manager of its Desktop Platforms Group, did say that 3GIO eventually would be optimized for the communications and embedded markets, where RapidIO now finds the lion's share of its adoption.

Cox expressed concern about the proliferation of I/O standards. "The customers of all of these technologies . . . don't want the market fragmented with a lot of standards. So, why do we need 3GIO? What can 3GIO do that RapidIO can't?"

He added that the PCI SIG's way should not be confused with "open" standards bodies. "I'm disappointed that this isn't being done in an open forum. You have to be invited to the party. With RapidIO or the IEEE, there is a call for papers, a call for participation. But PCI has always done things in isolation."

The Arapahoe Working Group plans to deliver a 1.0 spec to the PCI SIG in the first quarter, with a final specification approval slated for midyear 2002. Intel is already designing 3GIO into chip sets, the company said. Expect products that use the interconnect to be released late in 2003, although proliferation of the standard will take significantly longer.

High-level changes

While 3GIO will remain compatible with PCI software, many features of the high-speed serial interconnect will break from tradition. Higher-level changes include the use of switches in place of the multidrop bus, links in place of parallel buses, and prioritization of data packets as opposed to equal treatment of all data.

The interconnect's topology contains a host bridge and several end points, while multiple point-to-point connections introduce the switch into the I/O system. The switch, replacing the multidrop bus, provides fan-out for the I/O bus.

The switch would allow peer-to-peer communication between end points, and that traffic need not be forwarded to the host bridge, as long as it does not involve cache-coherent memory transfers. The switch could be used as a separate logical element or integrated into a host bridge component.

The parallel buses of current platforms would be replaced with 3GIO links with one or more lanes. Each link would be individually scalable by adding more lanes, meaning that additional bandwidth could be applied where required, such as graphics in the desktop platform and bus bridges (like 3GIO to PCI-X) in servers.

Different data types would be handled differently. Supporting both 32- and 64-bit memory addressing, packets would be tagged according to such attributes as "no-snoop," "relaxed ordering" and "priority," so that the I/O system could prioritize data flow. Each packet's unique identifier would allow response packets to be directed appropriately.

The architecture is divided into layers, with the physical, data link and transaction layers providing the "bottom" for legacy PCI software. The transaction layer would receive read and write requests from that software layer and create packets for transmission to the link layer. The transaction layer also receives response packets from the link layer and matches those with the original software requests.

PCI persists

3GIO's debut doesn't mean that PCI and PCI-X will go away anytime soon, said Roger Tipley, chairman of the PCI SIG. "PCI-X is going to be in servers forever because it serves a certain level of functionality, and it may not be compelling to switch to 3GIO for that functionality," Tipley said. "We learned that from not being able to get rid of ISA. ISA hung around because of all of these systems that weren't high-volume parts."

Tipley said the PCI SIG plans to fold Arapahoe, PCI-X double data rate (DDR) and PCI-X quad data rate (QDR) into a single work dubbed PCI 3.0. All can reside together, he said, although PCI-X may be affected by 3GIO in some applications. "We had some hopes that PCI-X would go further down in the food chain into desktops. We're seeing the need for Gigabit Ethernet from the desktop guys, and 3GIO is probably how they'd connect it."

PCI-X DDR, which should be delivered by the end of the year, and PCI-X QDR will be enabled by an Accelerated Graphics Port type of technology, Tipley said. Serving as stepping-stones toward 3GIO implementation, the standards look to fill in the performance blanks between PCI-X and 3GIO. "It takes PCI-X and utilizes what in essence is an AGP kind of phase-locked loop," Tipley said. "So you get two transfers per clock in DDR and four in quad. The clock's still 133 [MHz], but you get more than one 32- or 64-bit quantity transferred in every clock."

Commenting on the relationship between the PCI SIG and the Arapahoe Working Group, Tipley expressed concern over the perception that the SIG will endorse whatever Intel ordains. "We don't want something to show up on our doorstep that we can't take. If they give us something that's not what we want, we're not forced to take whatever they come up with," Tipley said. "We have to anoint it, but we won't do that automatically."

Surprisingly, Tipley said the PCI SIG had approached Intel about the ongoing work on the spec, not the other way around. And Intel's Bhatt said other industry bodies beside the PCI SIG had been approached for help.

"We brought this spec to other bodies, not just the PCI SIG. But I, as a technologist, was quite concerned about the bureaucracy. I wanted to follow the PCI-X model, to work with a small group of people who see the problem the way you see it," Bhatt said. "Roger [Tipley of the PCI SIG] was the force behind it. He said, 'If you come to us, we can get engaged early on.' "

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